Semiconductor device having multiwork function gate patterns

ABSTRACT

A semiconductor device includes a semiconductor substrate having a first area and a second area, and a first gate pattern on the first area and a second gate pattern on the second area. The first gate pattern includes a first gate insulating pattern on the first area, a first gate barrier pattern on the first gate insulating pattern, and a first work function metal pattern on the first gate barrier pattern. The second gate pattern includes a second gate insulating pattern on the second area, a second gate barrier pattern on the second gate insulating pattern, and a second work function metal pattern on the second gate barrier pattern. The first gate barrier pattern includes a metal material different than the second gate barrier pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This is a Continuation Application of U.S. application Ser. No. 15/017,filed Feb. 8, 2016, which claims priority under 35 U.S.C. §119 is madeto Korean Patent Application No. 10-2015-0079367 filed on Jun. 4, 2015,the entire contents of which are hereby incorporated by reference.

BACKGROUND

The present inventive concept relates to a semiconductor device havingmultiwork function gate patterns and a method of fabricating the same.

In view of the requirements of high integration and high operationspeed, gate insulating layers and gate electrodes of CMOS semiconductordevices are required to be ultra-thin. In order to overcome limitationson the physical dimensions of ultra-thin gate insulating layers andmanufacturing processes thereof, high-k gate insulating layers have beenused. In order to control the work function of semiconductor deviceshaving high-k gate insulating layers and metal gate structures, thethickness of barrier layers of the metal gate structures have beencontrolled. However, typical methods of controlling the thickness ofbarrier layers have become virtually impossible to carry out due to thereduced size of semiconductor devices.

SUMMARY

Embodiments of the inventive concept provide a semiconductor devicehaving multi-work function gate patterns.

Embodiments of the inventive concept provide a method of fabricating asemiconductor device having multi-work function gate patterns.

Embodiments of the inventive concept provide a semiconductor deviceincluding a semiconductor substrate having a first conductivity typetransistor area including a first area and a second area, and a firstgate pattern on the first region and a second gate pattern on the secondregion. The first gate pattern includes a first gate insulating patternon the first area, a first gate barrier pattern on the first gateinsulating pattern, and a first work function metal pattern on the firstgate barrier pattern. The second gate pattern may include a second gateinsulating pattern on the second area, a second gate barrier pattern onthe second gate insulating pattern, and a second work function metalpattern on the second gate barrier pattern. The first gate barrierpattern includes a different metal material than the second gate barrierpattern.

Embodiments of the inventive concept provide a semiconductor deviceincluding a semiconductor substrate having a first area in which a firstNMOS transistor is formed, a second area in which a second NMOStransistor having a different threshold voltage than the first NMOStransistor is formed, a third area in which a first PMOS transistor isformed, and a fourth area in which a second PMOS transistor having adifferent threshold voltage than the first PMOS transistor is formed,and a first NMOS gate pattern on the first area, a second NMOS gatepattern on the second area, a first PMOS gate pattern on the third area,and a second PMOS gate pattern on the fourth area. A first NMOS gatebarrier pattern of the first NMOS gate pattern includes a differentmetal material than a second NMOS gate barrier pattern of the secondNMOS gate pattern. A first PMOS gate barrier pattern of the first PMOSgate pattern includes a different metal material than a second PMOS gatebarrier pattern of the second PMOS gate pattern.

Embodiments of the inventive concept provide a semiconductor deviceincluding a semiconductor substrate including a first area having afirst NMOS transistor and a second area having a second NMOS transistorwhich has a different threshold voltage than the first NMOS transistor,a first gate insulating pattern on the first area and a second gateinsulating pattern on the second area, a first gate barrier pattern onthe first gate insulating pattern and a second gate barrier pattern onthe second gate insulating pattern, a first work function metal patternon the first gate barrier pattern and a second work function metalpattern on the second gate barrier pattern, and a first barrier cappingpattern on the first work function metal pattern and a second barriercapping pattern on the second work function metal pattern. The firstgate barrier pattern includes a metal material having a different workfunction than the second gate barrier pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features and advantages of the inventive conceptwill be apparent from the following description of embodiments of theinventive concept, as illustrated in the accompanying drawings in whichlike reference numerals denote the same respective parts throughout thedifferent views. The drawings are not necessarily to scale, emphasisinstead being placed upon illustrating the principles of the inventiveconcept. In the drawings:

FIG. 1 is a layout diagram illustrating a semiconductor device accordingto an embodiment of the inventive concept;

FIGS. 2A-2E, 3A-3E, and 4A-4E illustrate cross-sectional views takenalong lines I-I′, II-II′, III-III′, IV-IV′, V-V′, VI-VI′, VII-VII′, andVIII-VIII′ of FIG. 1 for describing a semiconductor device according tovarious embodiments of the inventive concept;

FIGS. 5A-5D, 6A-6F, and 7A-7F illustrate cross-sectional views takenalong lines I-I′, II-II′, V-V′ and VI-VI′ of FIG. 1 for describingmethods of fabricating a semiconductor device according to variousembodiments of the inventive concept;

FIG. 8 is a schematic diagram illustrating a semiconductor module,according to an embodiment of the inventive concept; and

FIG. 9 is a schematic block diagram illustrating an electronic system,according to an embodiment of the inventive concept.

FIG. 10 is a schematic block diagram illustrating an electronic system,according to an embodiment of the inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various embodiments of the inventive concept will now be described morefully with reference to the accompanying drawings. The inventive conceptdisclosed herein may, however, be embodied in different forms and shouldnot be construed as limited to the embodiments set forth herein. Rather,these embodiments are provided so that this disclosure is thorough andcomplete and fully conveys the inventive concept to those skilled in theart.

The terminology used herein to describe embodiments of the inventiveconcept is not intended to limit the scope of the inventive concept. Thearticles “a,” “an,” and “the” are singular in that they have a singlereferent; however, the use of the singular form in the present documentshould not preclude the presence of more than one referent. In otherwords, elements of the inventive concept referred to in the singularform may number one or more, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “includes,” and/or “including,” when used herein, specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

It should be understood that when an element or layer is referred to asbeing “on,” “connected to,” or “coupled to” another element or layer, itcan be directly on, connected to, or coupled to the other element orlayer or intervening elements or layers may be present. In contrast,when an element is referred to as being “directly on,” “directlyconnected to,” or “directly coupled to” another element or layer, thereare no intervening elements or layers present. In the followingexplanation, the same reference numerals denote the same componentsthroughout the specification.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper,” and the like may be used herein to describe the relationship ofone element or feature to another, as illustrated in the drawings. Itshould be understood that such descriptions are intended to encompassdifferent orientations in use or operation in addition to orientationsdepicted in the drawings. For example, if a device is turned over,elements described as “below” or “beneath” other elements or featureswould then be oriented “above” the other elements or features. Thus, theterm “below” is intended to mean both above and below, depending uponoverall device orientation.

Embodiments are described herein with reference to cross-sectionaland/or planar illustrations that are schematic illustrations ofidealized embodiments and intermediate structures. In the drawings, thesizes and relative sizes of layers and regions may be exaggerated forclarity. As such, variations from the shapes of the illustrations as aresult, for example, of manufacturing techniques and/or tolerances, areto be expected. Thus, embodiments should not be construed as limited tothe particular shapes of regions illustrated herein but are to includedeviations in shapes that result, for example, from manufacturing. Forexample, an implanted region illustrated as a rectangle will, typically,have rounded or curved features and/or a gradient of implantconcentration at its edges rather than a binary change from implanted tonon-implanted regions. Likewise, a buried region formed by implantationmay result in some implantation in the region between the buried regionand the surface through which the implantation takes place. Thus, theregions illustrated in the figures are schematic in nature and theirshapes are not intended to illustrate the actual shape of a region of adevice and are not intended to limit the scope of the present inventiveconcept.

Like numerals refer to like elements throughout the specification.Accordingly, the same numerals and similar numerals can be describedwith reference to other drawings, even if not specifically described ina corresponding drawing. Further, when a numeral is not marked in adrawing, the numeral can be described with reference to other drawings.

FIG. 1 is a layout diagram illustrating a semiconductor device,according to an embodiment of the inventive concept.

Referring to FIG. 1, the semiconductor device according to embodimentsof the inventive concept includes a substrate 11, active regions 20 onthe substrate 11, and gate patterns 30 crossing the active regions 20.The substrate 11 includes an NMOS area NA and a PMOS area PA. The NMOSarea NA includes a first NMOS area N1 and a second NMOS area N2. ThePMOS area PA includes a first PMOS area P1 and a second PMOS area P2.For example, the first NMOS area N1 may include an NMOS transistor thathas a low threshold voltage, and the second NMOS area N2 may include anNMOS transistor that has a high threshold voltage. Also, the first PMOSarea P1 may include a PMOS transistor that has a low threshold voltage,and the second PMOS area P2 may include a PMOS transistor that has ahigh threshold voltage.

FIG. 2A illustrates cross-sectional views taken along lines I-I′,II-II′, III-III′, and IV-IV′ of FIG. 1, and FIG. 2B illustratescross-sectional views taken along lines V-V′, VI-VI′, VII-VII′, andVIII-VIII′ of FIG. 1.

Referring to FIGS. 2A and 2B, a semiconductor device 100A in accordancewith embodiments of the inventive concept includes a substrate 101,device isolation regions 110 defining active regions 120 and 140 on thesubstrate 101, gate patterns 130A, 130B, 150A, and 150B on the activeregions 120 and 140.

The substrate 101 may include a single crystalline semiconductorsubstrate such as a silicon wafer or a silicon-on-insulator (SOI) wafer.As described above, the substrate 101 may include the NMOS area NAincluding the first NMOS area N1 in which the NMOS transistor that hasthe low threshold voltage is formed and the second NMOS area N2 in whichthe NMOS transistor that has the high threshold voltage is formed, andthe PMOS area PA including the first PMOS area P1 in which the PMOStransistor that has the low threshold voltage is formed and the secondPMOS area P2 in which the PMOS transistor that has the high thresholdvoltage is formed.

The active regions 120 and 140 may include first active regions 120 inthe NMOS area NA and second active regions 140 in the PMOS area PA. Thefirst active regions 120 may include first channel areas 125 verticallyoverlapping the gate patterns 130A and 130B and first source/drain areas127 not vertically overlapping the gate patterns 130A and 130B. Thefirst source/drain area 127 may include N-type impurities such asphosphorus (P) and/or arsenic (As). The first channel areas 125 mayinclude silicon (Si).

Further, the second active regions 140 may include second channel areas145 vertically overlapping the gate patterns 150A and 150B and secondsource/drain areas 147 not vertically overlapping the gate patterns 150Aand 150B. The second source/drain area 147 may include P-type impuritiessuch as boron (B). The second channel areas 145 may include silicongermanium (SiGe).

The device isolation regions 110 may be formed on the substrate 101 todefine the first active regions 120 and the second active regions 140.The device isolation regions 110 may include device isolation trenches111 that are formed in the substrate 101 and a device isolationinsulator 112 in the device isolation trenches 111. The device isolationinsulator 112 may include silicon oxide (SiO₂), silicon nitride (SiN),and/or silicon oxynitride (SiON).

The gate patterns 130A, 130B, 150A and 150B may include NMOS gatepatterns 130A and 130B in the NMOS area NA, and PMOS gate patterns 150Aand 150B in the PMOS area PA. The NMOS gate patterns 130A and 130B mayinclude a first NMOS gate pattern 130A in the first NMOS area N1 and asecond NMOS gate pattern 130B in the second NMOS area N2. Further, thePMOS gate patterns 150A and 150B may include a first PMOS gate pattern150A in the first PMOS area P1 and a second PMOS gate pattern 150B inthe second PMOS area P2.

The first NMOS gate pattern 130A includes an NMOS interfacial insulatingpattern 131, an NMOS gate insulating pattern 132, a first NMOS gatebarrier pattern 133, an NMOS work function metal pattern 135, an NMOSbarrier capping pattern 136, and an NMOS gate electrode pattern 137. Thesecond NMOS gate pattern 130B includes an NMOS interfacial insulatingpattern 131, an NMOS gate insulating pattern 132, a second NMOS gatebarrier pattern 134, an NMOS work function metal pattern 135, an NMOSbarrier capping pattern 136, and an NMOS gate electrode pattern 137.

The NMOS interfacial insulating pattern 131 may be formed on surfaces ofthe first active regions 120. The NMOS interfacial insulating pattern131 may include at least one of a natural oxide layer formed on thesurfaces of the first active regions 120, a silicon oxide layer formedusing a thermal oxidation process, and a silicon oxide layer depositedusing a deposition process such as an atomic layer deposition (ALD)process.

The NMOS gate insulating pattern 132 may be conformally formed on asurface of the NMOS interfacial insulating pattern 131 and a surface ofthe device isolation region 110. The NMOS gate insulating pattern 132may include at least one of high-k dielectric insulators, such ashafnium oxide (HfO), aluminum oxide (AlO), zirconium oxide (ZrO),lanthanum oxide (LaO), or another metal oxide.

The first NMOS gate barrier pattern 133 and the second NMOS gate barrierpattern 134 may be conformally formed on the NMOS gate insulatingpatterns 132, respectively. For example, the first NMOS gate barrierpattern 133 may be conformally formed on the NMOS gate insulatingpattern 132 in the first NMOS area N1, and the second NMOS gate barrierpattern may be conformally formed on the NMOS gate insulating pattern132 in the second NMOS area N2.

The first NMOS gate barrier pattern 133 and the second NMOS gate barrierpattern 134 may include at least one of titanium nitride (TiN), tantalumnitride (TaN), titanium oxynitride (TiON), tantalum oxynitride (TaON),titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN),titanium silicon nitride (TiSiN), titanium aluminum oxynitride (TiAlON),tantalum aluminum oxynitride (TaAlON), and titanium silicon oxynitride(TiSiON).

The first NMOS gate barrier pattern 133 may include a metal materialdifferent than the second NMOS gate barrier pattern 134. A work functionof the first NMOS gate barrier pattern 133 may be different than a workfunction of the second NMOS gate barrier pattern 134. For example, thework function of the first NMOS gate barrier pattern 133 may be smallerthan the work function of the second NMOS gate barrier pattern 134. Forexample, in embodiments of the inventive concept, the first NMOS gatebarrier pattern 133 may include titanium nitride (TiN), and the secondNMOS gate barrier pattern 134 may include titanium silicon nitride(TiSiN).

The NMOS work function metal pattern 135 may be conformally formed onthe first NMOS gate barrier pattern 133 and the second NMOS gate barrierpattern 134. The NMOS work function metal pattern 135 may include atleast one of titanium aluminum (TiAl), titanium aluminum oxide (TiAlO),titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN),titanium aluminum oxynitride (TiAlON), titanium aluminum carbonitride(TiAlCN), titanium aluminum oxycarbonitride (TiAlOCN), and a combinationthereof.

The NMOS barrier capping pattern 136 may be conformally formed on theNMOS work function metal pattern 135. The NMOS barrier capping pattern136 may include at least one of titanium nitride (TiN), tantalum nitride(TaN), titanium oxynitride (TiON), tantalum oxynitride (TaON), titaniumaluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titaniumsilicon nitride (TiSiN), titanium aluminum oxynitride (TiAlON), tantalumaluminum oxynitride (TaAlON), and titanium silicon oxynitride (TiSiON).

The NMOS gate electrode pattern 137 may be formed on the NMOS barriercapping pattern 136. The NMOS gate electrode pattern 137 may include atleast one of titanium nitride (TiN), tantalum nitride (TaN), tungsten(W), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), andnickel-platinum alloy (Ni—Pt).

The first PMOS gate pattern 150A includes a PMOS interfacial insulatingpattern 151, a PMOS gate insulating pattern 152, a first PMOS gatebarrier pattern 153, a PMOS work function metal pattern 155, a PMOSbarrier capping pattern 156, and a PMOS gate electrode pattern 157. Thesecond PMOS gate pattern 150B includes a PMOS interfacial insulatingpattern 151, a PMOS gate insulating pattern 152, a second PMOS gatebarrier pattern 154, a PMOS work function metal pattern 155, a PMOSbarrier capping pattern 156, and a PMOS gate electrode pattern 157.

The PMOS interfacial insulating pattern 151 may be formed on surfaces ofthe second active regions 140. The PMOS interfacial insulating pattern151 may include at least one of a natural oxide layer formed on thesurfaces of the second active regions 140, a silicon oxide layer formedusing a thermal oxidation process, and silicon oxide layer depositedusing a deposition process such as an ALD process.

The PMOS gate insulating pattern 152 may be conformally formed on asurface of the PMOS interfacial insulating pattern 151 and a surface ofthe device isolation region 110. The PMOS gate insulating pattern 152may include at least one of high-k dielectric insulators, such ashafnium oxide (HfO), aluminum oxide (AlO), zirconium oxide (ZrO),lanthanum oxide (LaO), or another metal oxide.

The first PMOS gate barrier pattern 153 and the second PMOS gate barrierpattern 154 may be conformally formed on the PMOS gate insulatingpatterns 152, respectively. For example, the first PMOS gate barrierpattern 153 may be conformally formed on the PMOS gate insulatingpattern 152 in the first PMOS area P1, and the second PMOS gate barrierpattern 154 may be conformally formed on the PMOS gate insulatingpattern 152 in the second PMOS area P2.

The first PMOS gate barrier pattern 153 and the second PMOS gate barrierpattern 154 may include at least one of titanium nitride (TiN), tantalumnitride (TaN), titanium oxynitride (TiON), tantalum oxynitride (TaON),titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN),titanium silicon nitride (TiSiN), titanium aluminum oxynitride (TiAlON),tantalum aluminum oxynitride (TaAlON), and titanium silicon oxynitride(TiSiON).

In embodiments of the inventive concept, the first PMOS gate barrierpattern 153 may include a metal material different than the second PMOSgate barrier pattern 154. For example, the first PMOS gate barrierpattern 153 may include titanium silicon nitride (TiSiN), and the secondPMOS gate barrier pattern 154 may include titanium nitride (TiN). A workfunction of the first PMOS gate barrier pattern 153 may be differentthan a work function of the second PMOS gate barrier pattern 154. Forexample, the work function of the first PMOS gate barrier pattern 153may be greater than the work function of the second PMOS gate barrierpattern 154.

Further, in embodiments of the inventive concept, the first PMOS gatebarrier pattern 153 may include the same metal material as the secondNMOS gate barrier pattern 134, and the second PMOS gate barrier pattern154 may include the same metal material as the first NMOS gate barrierpattern 133. That is, the work function of the first PMOS gate barrierpattern 153 may be the same as the work function of the second NMOS gatebarrier pattern 134, and the work function of the second PMOS gatebarrier pattern 154 may be the same as the work function of the firstNMOS gate barrier pattern 133, but the present inventive concept is notlimited thereto.

The PMOS work function metal pattern 155 may be conformally formed onthe first PMOS gate barrier pattern 153 and the second PMOS gate barrierpattern 154. The PMOS work function metal pattern 155 may include atleast one of titanium aluminum (TiAl), titanium aluminum oxide (TiAlO),titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN),titanium aluminum oxynitride (TiAlON), titanium aluminum carbonitride(TiAlCN), titanium aluminum oxycarbonitride (TiAlOCN), and a combinationthereof.

The PMOS barrier capping pattern 156 may be conformally formed on thePMOS work function metal pattern 155. The PMOS barrier capping pattern156 may include at least one of titanium nitride (TiN), tantalum nitride(TaN), titanium oxynitride (TiON), tantalum oxynitride (TaON), titaniumaluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titaniumsilicon nitride (TiSiN), titanium aluminum oxynitride (TiAlON), tantalumaluminum oxynitride (TaAlON), and titanium silicon oxynitride (TiSiON).

The PMOS gate electrode pattern 157 may be formed on the PMOS barriercapping pattern 156. The PMOS gate electrode pattern 157 may include atleast one of titanium nitride (TiN), tantalum nitride (TaN), tungsten(W), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), andnickel-platinum alloy (Ni—Pt).

As described above, the semiconductor device 100A according toembodiments of the inventive concept may include gate barrier patternsincluding metal materials that have the different work functions fromeach other. As a result, gate patterns having different effective workfunctions can be formed in one area.

FIG. 2C illustrates cross-sectional views taken along lines I-I′,II-II′, III-III′, and IV-IV′ of FIG. 1. In this embodiment of theinventive concept, detailed descriptions of the same contents as thoseof the above-described embodiments will be omitted.

Referring to FIG. 2C, the semiconductor device 100B in accordance withembodiments of the inventive concept may include a first NMOS gatepattern 130A having a multi-layer first NMOS gate barrier pattern 133, asecond NMOS gate pattern 130B having a multi-layer second NMOS gatebarrier pattern 134, a first PMOS gate pattern 150A having a multi-layerfirst PMOS gate barrier pattern 153, and a second PMOS gate pattern 150Bhaving a multi-layer second PMOS gate barrier pattern 154, compared tothe semiconductor device 100A in FIGS. 2A and 2B.

The first NMOS gate barrier pattern 133 may include a first lower NMOSgate barrier pattern 133 a on an NMOS gate insulating pattern 132 in afirst NMOS area N1, a first intermediate NMOS gate barrier pattern 133 bon the first lower NMOS gate barrier pattern 133 a, and a first upperNMOS gate barrier pattern 133 c on the first intermediate NMOS gatebarrier pattern 133 b. Further, the second NMOS gate barrier pattern 134may include a second lower NMOS gate barrier pattern 134 a on an NMOSgate insulating pattern 132 in a second NMOS area N2, a secondintermediate NMOS gate barrier pattern 134 b on the second lower NMOSgate barrier pattern 134 a, and a second upper NMOS gate barrier pattern134 c on the second intermediate NMOS gate barrier pattern 134 b.

The first lower NMOS gate barrier pattern 133 a may include a metalmaterial different than the second lower NMOS gate barrier pattern 134a. For example, the first lower NMOS gate barrier pattern 133 a mayinclude titanium nitride (TiN), and the second lower NMOS gate barrierpattern 134 a may include titanium silicon nitride (TiSiN).

The first intermediate NMOS gate barrier pattern 133 b and the secondintermediate NMOS gate barrier pattern 134 b may include the same metalmaterial. Also, the first upper NMOS gate barrier pattern 133 c and thesecond upper NMOS gate barrier pattern 134 c may include the same metalmaterial. For example, the first intermediate NMOS gate barrier pattern133 b, the second intermediate NMOS gate barrier pattern 134 b, thefirst upper NMOS gate barrier pattern 133 c and the second upper NMOSgate barrier pattern 134 c may include titanium nitride (TiN) ortantalum nitride (TaN). The first intermediate NMOS gate barrier pattern133 b may include a metal material different than the first upper NMOSgate barrier pattern 133 c. Further, the second intermediate NMOS gatebarrier pattern 134 b may include a metal material different than thesecond upper NMOS gate barrier pattern 134 c.

The first PMOS gate barrier pattern 153 may include a first lower PMOSgate barrier pattern 153 a on a PMOS gate insulating pattern 152 in afirst PMOS area P1, a first intermediate PMOS gate barrier pattern 153 bon the first lower PMOS gate barrier pattern 153 a, and a first upperPMOS gate barrier pattern 153 c on the first intermediate PMOS gatebarrier pattern 153 b. Further, the second PMOS gate barrier pattern 154may include a second lower PMOS gate barrier pattern 154 a on a PMOSgate insulating pattern 152 in a second PMOS area P2, a secondintermediate PMOS gate barrier pattern 154 b on the second lower PMOSgate barrier pattern 154 a, and a second upper PMOS gate barrier pattern154 c on the second intermediate PMOS gate barrier pattern 154 b.

The first lower PMOS gate barrier pattern 153 a may include a metalmaterial different than the second lower PMOS gate barrier pattern 154a. For example, the first lower PMOS gate barrier pattern 153 a mayinclude titanium silicon nitride (TiSiN), and the second lower PMOS gatebarrier pattern 154 a may include titanium nitride (TiN).

The first intermediate PMOS gate barrier pattern 153 b and the secondintermediate PMOS gate barrier pattern 154 b may include the same metalmaterial. Also, the first upper PMOS gate barrier pattern 153 c and thesecond upper PMOS gate barrier pattern 154 c may include the same metalmaterial. For example, the first intermediate PMOS gate barrier pattern153 b, the second intermediate PMOS gate barrier pattern 154 b, thefirst upper PMOS gate barrier pattern 153 c and the second upper PMOSgate barrier pattern 154 c may include titanium nitride (TiN) ortantalum nitride (TaN). The first intermediate PMOS gate barrier pattern153 b may include a metal material different than the first upper PMOSgate barrier pattern 153 c. Further, the second intermediate PMOS gatebarrier pattern 154 b may include a metal material different than thesecond upper PMOS gate barrier pattern 154 c.

FIG. 2D illustrates cross-sectional views taken along lines I-I′,II-II′, III-III′, and IV-IV′ of FIG. 1. In this embodiment of theinventive concept, detailed descriptions of the same contents as thoseof the above-described embodiments will be omitted.

Referring to FIG. 2D, in the semiconductor device 100C in accordancewith embodiments of the inventive concept, a first upper NMOS gatebarrier pattern 133 c and a second upper NMOS gate barrier pattern 134 chave different metal materials, and a first upper PMOS gate barrierpattern 153 c and a second upper PMOS gate barrier pattern 154 c havedifferent metal materials, compared to the semiconductor device 100B inFIG. 2C.

Further, the first lower NMOS gate barrier pattern 133 a and the secondlower NMOS gate barrier pattern 134 a may include the same metalmaterial, and the first intermediate NMOS gate barrier pattern 133 b andthe second intermediate NMOS gate barrier pattern 134 b may include thesame metal material.

Also, the first lower PMOS gate barrier pattern 153 a and the secondlower PMOS gate barrier pattern 154 a may include the same metalmaterial, and the first intermediate PMOS gate barrier pattern 153 b andthe second intermediate PMOS gate barrier pattern 154 b may include thesame metal material.

FIG. 2E illustrates cross-sectional views taken along lines I-I′,II-II′, III-III′, and IV-IV′ of FIG. 1. In this embodiment of theinventive concept, detailed descriptions of the same contents as thoseof the above-described embodiments will be omitted.

Referring to FIG. 2E, in the semiconductor device 100D in accordancewith embodiments of the inventive concept, a first intermediate NMOSgate barrier pattern 133 b and a second intermediate NMOS gate barrierpattern 134 b have different metal materials, and a first intermediatePMOS gate barrier pattern 153 b and a second intermediate PMOS gatebarrier pattern 154 b have different metal materials, compared to thesemiconductor device 100B in FIG. 2C.

Further, the first lower NMOS gate barrier pattern 133 a and the secondlower NMOS gate barrier pattern 134 a may include the same metalmaterial, and the first upper NMOS gate barrier pattern 133 c and thesecond upper NMOS gate barrier pattern 134 c may include the same metalmaterial.

Also, the first lower PMOS gate barrier pattern 153 a and the secondlower PMOS gate barrier pattern 154 a may include the same metalmaterial, and the first upper PMOS gate barrier pattern 153 c and thesecond upper PMOS gate barrier pattern 154 c may include the same metalmaterial.

FIG. 3A illustrates cross-sectional views taken along lines I-I′,II-II′, III-III′, and IV-IV′ of FIG. 1, and FIG. 3B illustratescross-sectional views taken along lines V-V′, VI-VI′, VII-VII′, andVIII-VII′ of FIG. 1. In this embodiment of the inventive concept,detailed descriptions of the same contents as those of theabove-described embodiments will be omitted.

Referring to FIGS. 3A and 3B, the semiconductor device 200A inaccordance with embodiments of the inventive concept may include gatepatterns 230A, 230B, 250A and 250B including a first NMOS gate pattern230A in a first NMOS area N1, a second NMOS gate pattern 230B in asecond NMOS area N2, a first PMOS gate pattern 250A in a first PMOS areaP1, and a second PMOS gate pattern 250B in a second PMOS area P2.

A substrate 201 may include a NMOS area NA including the first NMOS areaN1 in which the NMOS transistor that has the low threshold voltage isformed and the second NMOS area N2 in which the NMOS transistor that hasthe high threshold voltage is formed, and a PMOS area PA including thefirst PMOS area P1 in which the PMOS transistor that has the lowthreshold voltage is formed and the second PMOS area P2 in which thePMOS transistor that has the high threshold voltage is formed.

The first NMOS gate pattern 230A includes an NMOS interfacial insulatingpattern 231 on the substrate 201, an NMOS gate insulating pattern 232formed on the NMOS interfacial insulating pattern 231 in a U-shape, afirst NMOS gate barrier pattern 233 formed on the NMOS gate insulatingpattern 232 in a U-shape, an NMOS work function metal pattern 235 formedon the first NMOS gate barrier pattern 233 in a U-shape, an NMOS barriercapping pattern 236 on the NMOS work function metal pattern 235 in aU-shape, and an NMOS gate electrode pattern 237 formed on the NMOSbarrier capping pattern 236. Upper surfaces of the NMOS gate insulatingpattern 232, the first NMOS gate barrier pattern 233, the NMOS workfunction metal pattern 235, the NMOS barrier capping pattern 236, andthe NMOS gate electrode pattern 237 may be substantially coplanar.

The second NMOS gate pattern 230B includes an NMOS interfacialinsulating pattern 231 on the substrate 201, an NMOS gate insulatingpattern 232 formed on the NMOS interfacial insulating pattern 231 in aU-shape, a second NMOS gate barrier pattern 234 formed on the NMOS gateinsulating pattern 232 in a U-shape, an NMOS work function metal pattern235 formed on the second NMOS gate barrier pattern 234 in a U-shape, anNMOS barrier capping pattern 236 on the NMOS work function metal pattern235 in a U-shape, and an NMOS gate electrode pattern 237 formed on theNMOS barrier capping pattern 236. Upper surfaces of the NMOS gateinsulating pattern 232, the second NMOS gate barrier pattern 234, theNMOS work function metal pattern 235, the NMOS barrier capping pattern236, and the NMOS gate electrode pattern 237 may be substantiallycoplanar.

The first PMOS gate pattern 250A includes a PMOS interfacial insulatingpattern 251 on the substrate 201, a PMOS gate insulating pattern 252formed on the PMOS interfacial insulating pattern 251 in a U-shape, afirst PMOS gate barrier pattern 253 formed on the PMOS gate insulatingpattern 252 in a U-shape, a PMOS work function metal pattern 255 formedon the first PMOS gate barrier pattern 253 in a U-shape, a PMOS barriercapping pattern 256 on the PMOS work function metal pattern 255 in aU-shape, and a PMOS gate electrode pattern 257 formed on the PMOSbarrier capping pattern 256. Upper surfaces of the PMOS gate insulatingpattern 252, the first PMOS gate barrier pattern 253, the PMOS workfunction metal pattern 255, the PMOS barrier capping pattern 256, andthe PMOS gate electrode pattern 257 may be substantially coplanar.

The second PMOS gate pattern 250B includes a PMOS interfacial insulatingpattern 251 on a substrate 201, a PMOS gate insulating pattern 252formed on the PMOS interfacial insulating pattern 251 in a U-shape, asecond PMOS gate barrier pattern 254 formed on the PMOS gate insulatingpattern 252 in a U-shape, a PMOS work function metal pattern 255 formedon the second PMOS gate barrier pattern 254 in a U-shape, a PMOS barriercapping pattern 256 on the PMOS work function metal pattern 255 in aU-shape, and a PMOS gate electrode pattern 257 formed on the PMOSbarrier capping pattern 256. Upper surfaces of the PMOS gate insulatingpattern 252, the second PMOS gate barrier pattern 254, the PMOS workfunction metal pattern 255, the PMOS barrier capping pattern 256, andthe PMOS gate electrode pattern 257 may be substantially coplanar.

The semiconductor device 200A may further include a gate spacer 260 onsidewalls of the gate patterns 230A, 230B, 250A and 250B and aninterlayer insulating layer 270 covering an outer sidewall of gatespacer 260 and source/drain areas 227 and 247. The gate spacer 260 mayinclude at least one of silicon nitride (SiN), silicon oxynitride(SiON), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), andsilicon boron carbonitride (SiBCN). The interlayer insulating layer 270may include silicon oxide (SiO₂).

FIG. 3C illustrates cross-sectional views taken along lines I-I′,II-II′, III-III′, and IV-IV′ of FIG. 1. In this embodiment of theinventive concept, detailed descriptions of the same contents as thoseof the above-described embodiments will be omitted.

Referring to FIG. 3C, the semiconductor device 200B in accordance withembodiments of the inventive concept may include a first NMOS gatepattern 230A having a multi-layer first NMOS gate barrier pattern 233, asecond NMOS gate pattern 230B having a multi-layer second NMOS gatebarrier pattern 234, a first PMOS gate pattern 250A having a multi-layerfirst PMOS gate barrier pattern 253, and a second PMOS gate pattern 250Bhaving a multi-layer second PMOS gate barrier pattern 254, compared tothe semiconductor device 200A in FIG. 3A.

The first NMOS gate barrier pattern 233 may include a first lower NMOSgate barrier pattern 233 a on an NMOS gate insulating pattern 232 in afirst NMOS area N1, a first intermediate NMOS gate barrier pattern 233 bon the first lower NMOS gate barrier pattern 233 a, and a first upperNMOS gate barrier pattern 233 c on the first intermediate NMOS gatebarrier pattern 233 b. Further, the second NMOS gate barrier pattern 234may include a second lower NMOS gate barrier pattern 234 a on an NMOSgate insulating pattern 232 in a second NMOS area N2, a secondintermediate NMOS gate barrier pattern 234 b on the second lower NMOSgate barrier pattern 234 a, and a second upper NMOS gate barrier pattern234 c on the second intermediate NMOS gate barrier pattern 234 b.

The first lower NMOS gate barrier pattern 233 a may include a metalmaterial different than the second lower NMOS gate barrier pattern 234a. The first intermediate NMOS gate barrier pattern 233 b and the secondintermediate NMOS gate barrier pattern 234 b may include the same metalmaterial. Also, the first upper NMOS gate barrier pattern 233 c and thesecond upper NMOS gate barrier pattern 234 c may include the same metalmaterial.

The first PMOS gate barrier pattern 253 may include a first lower PMOSgate barrier pattern 253 a on a PMOS gate insulating pattern 252 in afirst PMOS area P1, a first intermediate PMOS gate barrier pattern 253 bon the first lower PMOS gate barrier pattern 253 a, and a first upperPMOS gate barrier pattern 253 c on the first intermediate PMOS gatebarrier pattern 253 b. Further, the second PMOS gate barrier pattern 254may include a second lower PMOS gate barrier pattern 254 a on a PMOSgate insulating pattern 252 in a second PMOS area P2, a secondintermediate PMOS gate barrier pattern 254 b on the second lower PMOSgate barrier pattern 254 a, and a second upper PMOS gate barrier pattern254 c on the second intermediate PMOS gate barrier pattern 254 b.

The first lower PMOS gate barrier pattern 253 a may include a metalmaterial different than the second lower PMOS gate barrier pattern 254a. The first intermediate PMOS gate barrier pattern 253 b and the secondintermediate PMOS gate barrier pattern 254 b may include the same metalmaterial. Also, the first upper PMOS gate barrier pattern 253 c and thesecond upper PMOS gate barrier pattern 254 c may include the same metalmaterial.

FIG. 3D illustrates cross-sectional views taken along lines I-I′,II-II′, III-III′, and IV-IV′ of FIG. 1. In this embodiment of theinventive concept, detailed descriptions of the same content as those ofthe above-described embodiments will be omitted.

Referring to FIG. 3D, in the semiconductor device 200C in accordancewith embodiments of the inventive concept, a first upper NMOS gatebarrier pattern 233 c and a second upper NMOS gate barrier pattern 234 chave different metal materials, and a first upper PMOS gate barrierpattern 253 c and a second upper PMOS gate barrier pattern 254 c havedifferent metal materials, compared to the semiconductor device 200B inFIG. 3C.

Further, the first lower NMOS gate barrier pattern 233 a and the secondlower NMOS gate barrier pattern 234 a may include the same metalmaterial, and the first intermediate NMOS gate barrier pattern 233 b andthe second intermediate NMOS gate barrier pattern 234 b may include thesame metal material.

Also, the first lower PMOS gate barrier pattern 253 a and the secondlower PMOS gate barrier pattern 254 a may include the same metalmaterial, and the first intermediate PMOS gate barrier pattern 253 b andthe second intermediate PMOS gate barrier pattern 254 b may include thesame metal material.

FIG. 3E illustrates cross-sectional views taken along lines I-I′,II-II′, III-III′, and IV-IV′ of FIG. 1. In this embodiment of theinventive concept, detailed descriptions of the same content as those ofthe above-described embodiments will be omitted.

Referring to FIG. 3E, in the semiconductor device 200D in accordancewith embodiments of the inventive concept, a first intermediate NMOSgate barrier pattern 233 b and a second intermediate NMOS gate barrierpattern 234 b have different metal materials, and a first intermediatePMOS gate barrier pattern 253 b and a second intermediate PMOS gatebarrier pattern 254 b have different metal materials, compared to thesemiconductor device 200B in FIG. 3C.

Further, the first lower NMOS gate barrier pattern 233 a and the secondlower NMOS gate barrier pattern 234 a may include the same metalmaterial, and the first upper NMOS gate barrier pattern 233 c and thesecond upper NMOS gate barrier pattern 234 c may include the same metalmaterial.

Also, the first lower PMOS gate barrier pattern 253 a and the secondlower PMOS gate barrier pattern 254 a may include the same metalmaterial, and the first upper PMOS gate barrier pattern 253 c and thesecond upper PMOS gate barrier pattern 254 c may include the same metalmaterial.

FIG. 4A illustrates cross-sectional views taken along lines I-I′,II-II′, III-III′, and IV-IV′ of FIG. 1, and FIG. 4B illustratescross-sectional views taken along lines V-V′, VI-VI′, VII-VII′, andVIII-VII′ of FIG. 1. In this embodiment of the inventive concept,detailed descriptions of the same contents as those of theabove-described embodiments will be omitted.

Referring to FIGS. 4A and 4B, the semiconductor device 300A inaccordance with embodiments of the inventive concept may include activeregions 320 and 340 having a fin shape protruding from a substrate 301,compared to the semiconductor device 200A in FIGS. 3A and 3B. Uppersurface of a device isolation region 310 formed on the substrate 301 maybe located at a lower level than upper surfaces of the active regions320 and 340. Accordingly, portions of the active regions 320 and 340 mayprotrude from the upper surface of the device isolation region 310.Upper and side surfaces of the active regions 320 and 340 protrudingfrom the upper surface of the device isolation region 310 may be coveredby gate patterns 330A, 330B, 350A, and 350B.

FIG. 4C illustrates cross-sectional views taken along lines I-I′,II-II′, III-III′, and IV-IV′ of FIG. 1. In this embodiment of theinventive concept, detailed descriptions of the same contents as thoseof the above-described embodiments will be omitted.

Referring to FIG. 4C, the semiconductor device 300B in accordance withembodiments of the inventive concept may include a first NMOS gatepattern 330A having a multi-layer first NMOS gate barrier pattern 333, asecond NMOS gate pattern 330B having a multi-layer second NMOS gatebarrier pattern 334, a first PMOS gate pattern 350A having a multi-layerfirst PMOS gate barrier pattern 353, and a second PMOS gate pattern 350Bhaving a multi-layer second PMOS gate barrier pattern 354, compared tothe semiconductor device 300A in FIG. 4A.

The first NMOS gate barrier pattern 333 may include a first lower NMOSgate barrier pattern 333 a on an NMOS gate insulating pattern 332 in afirst NMOS area N1, a first intermediate NMOS gate barrier pattern 333 bon the first lower NMOS gate barrier pattern 333 a, and a first upperNMOS gate barrier pattern 333 c on the first intermediate NMOS gatebarrier pattern 333 b. Further, the second NMOS gate barrier pattern 334may include a second lower NMOS gate barrier pattern 334 a on an NMOSgate insulating pattern 332 in a second NMOS area N2, a secondintermediate NMOS gate barrier pattern 334 b on the second lower NMOSgate barrier pattern 334 a, and a second upper NMOS gate barrier pattern334 c on the second intermediate NMOS gate barrier pattern 334 b.

The first lower NMOS gate barrier pattern 333 a may include a metalmaterial different than the second lower NMOS gate barrier pattern 334a. The first intermediate NMOS gate barrier pattern 333 b and the secondintermediate NMOS gate barrier pattern 334 b may include the same metalmaterial. Also, the first upper NMOS gate barrier pattern 333 c and thesecond upper NMOS gate barrier pattern 334 c may include the same metalmaterial.

The first PMOS gate barrier pattern 353 may include a first lower PMOSgate barrier pattern 353 a on a PMOS gate insulating pattern 352 in afirst PMOS area P1, a first intermediate PMOS gate barrier pattern 353 bon the first lower PMOS gate barrier pattern 353 a, and a first upperPMOS gate barrier pattern 353 c on the first intermediate PMOS gatebarrier pattern 353 b. Further, the second PMOS gate barrier pattern 354may include a second lower PMOS gate barrier pattern 354 a on a PMOSgate insulating pattern 352 in a second PMOS area P2, a secondintermediate PMOS gate barrier pattern 354 b on the second lower PMOSgate barrier pattern 354 a, and a second upper PMOS gate barrier pattern354 c on the second intermediate PMOS gate barrier pattern 354 b.

The first lower PMOS gate barrier pattern 353 a may include a metalmaterial different than the second lower PMOS gate barrier pattern 354a. The first intermediate PMOS gate barrier pattern 353 b and the secondintermediate PMOS gate barrier pattern 354 b may include the same metalmaterial. Also, the first upper PMOS gate barrier pattern 353 c and thesecond upper PMOS gate barrier pattern 354 c may include the same metalmaterial.

FIG. 4D illustrates cross-sectional views taken along lines I-I′,II-II′, III-III′, and IV-IV′ of FIG. 1. In this embodiment of theinventive concept, detailed descriptions of the same contents as thoseof the above-described embodiments will be omitted.

Referring to FIG. 4D, in the semiconductor device 300C in accordancewith embodiments of the inventive concept, a first upper NMOS gatebarrier pattern 333 c and a second upper NMOS gate barrier pattern 334 chave different metal materials, and a first upper PMOS gate barrierpattern 353 c and a second upper PMOS gate barrier pattern 354 c havedifferent metal materials, compared to the semiconductor device 300B inFIG. 4C.

Further, the first lower NMOS gate barrier pattern 333 a and the secondlower NMOS gate barrier pattern 334 a may include the same metalmaterial, and the first intermediate NMOS gate barrier pattern 333 b andthe second intermediate NMOS gate barrier pattern 334 b may include thesame metal material.

Also, the first lower PMOS gate barrier pattern 353 a and the secondlower PMOS gate barrier pattern 354 a may include the same metalmaterial, and the first intermediate PMOS gate barrier pattern 353 b andthe second intermediate PMOS gate barrier pattern 354 b may include thesame metal material.

FIG. 4E illustrates cross-sectional views taken along lines I-I′,II-II′, III-III′, and IV-IV′ of FIG. 1. In this embodiment of theinventive concept, detailed descriptions of the same content as those ofthe above-described embodiments will be omitted.

Referring to FIG. 4E, in the semiconductor device 300D in accordancewith embodiments of the inventive concept, a first intermediate NMOSgate barrier pattern 333 b and a second intermediate NMOS gate barrierpattern 334 b have different metal materials, and a first intermediatePMOS gate barrier pattern 353 b and a second intermediate PMOS gatebarrier pattern 354 b have different metal materials, compared to thesemiconductor device 300B in FIG. 4C.

Further, the first lower NMOS gate barrier pattern 333 a and the secondlower NMOS gate barrier pattern 334 a may include the same metalmaterial, and the first upper NMOS gate barrier pattern 333 c and thesecond upper NMOS gate barrier pattern 334 c may include the same metalmaterial.

Also, the first lower PMOS gate barrier pattern 353 a and the secondlower PMOS gate barrier pattern 354 a may include the same metalmaterial, and the first upper PMOS gate barrier pattern 353 c and thesecond upper PMOS gate barrier pattern 354 c may include the same metalmaterial.

FIGS. 5A to 5D illustrate cross-sectional views taken along lines I-I′,II-II′, V-V′, and VI-VI′ of FIG. 1. FIGS. 5A to 5D are views regardingonly an NMOS area, but it may be simultaneously or separately performedin the same method with respect to a PMOS area.

Referring to FIG. 5A, a method of fabricating the semiconductor devicein accordance with embodiments of the inventive concept may includepreparing a substrate 101, forming device isolation regions 110 definingactive regions 120 on the substrate 101, sequentially forming aninterfacial insulating layer 1, a gate insulating layer 2, and a firstgate barrier layer 3 on surfaces of the active regions 120 and surfacesof the device isolation regions 110, and forming a first mask pattern M1on the first gate barrier layer 3.

The substrate 101 may include a single crystalline semiconductorsubstrate such as a silicon wafer or SOI wafer. The substrate 101 mayinclude a first NMOS area N1 in which the NMOS transistor having a lowthreshold voltage is disposed, and the second NMOS area N2 in which theNMOS transistor having a high threshold voltage is disposed.

The forming of the device isolation regions 110 defining the activeregions 120 may include performing a shallow trench isolation (STI)process. The STI process may include forming device isolation trenches111 in the substrate 101, and filling the device isolation trenches 111with a device isolation insulator 112. The device isolation insulator112 may include silicon oxide (SiO₂), silicon nitride (SiN), and/orsilicon oxynitride (SiON).

The interfacial insulating layer 1 may be conformally formed on theactive regions 120. The interfacial insulating layer 1 may include atleast one of a natural oxide layer formed on the surfaces of the firstactive regions 120, a silicon oxide layer formed using a thermaloxidation process, and a silicon oxide layer deposited using adeposition process such as an ALD process. When the interfacialinsulating layer 1 is formed by the ALD process, the interfacialinsulating layer 1 may be conformally formed on the device isolationregions 110 in addition to the active regions 120. In other embodiments,the interfacial insulating layer 1 may be omitted.

The gate insulating layer 2 may be conformally formed on the interfacialinsulating layer 1 and the device isolation regions 110 by performing adeposition process. The gate insulating layer 2 may include at least oneof high-k dielectric insulators, such as hafnium oxide (HfO), aluminumoxide (AlO), zirconium oxide (ZrO), lanthanum oxide (LaO), and anothermetal oxide.

The first gate barrier layer 3 may be conformally formed on the gateinsulating layer 2 by performing a deposition process. The first gatebarrier layer 3 may include at least one of titanium nitride (TiN),tantalum nitride (TaN), titanium oxynitride (TiON), tantalum oxynitride(TaON), titanium aluminum nitride (TiAlN), tantalum aluminum nitride(TaAlN), titanium silicon nitride (TiSiN), titanium aluminum oxynitride(TiAlON), tantalum aluminum oxynitride (TaAlON), and titanium siliconoxynitride (TiSiON). As an example, the first gate barrier layer 3 mayinclude TiN. The deposition process may include an ALD or a chemicalvapor deposition (CVD) process.

The first mask pattern M1 may be formed to expose the first gate barrierlayer 3 of the second NMOS area N2 and cover the first gate barrierlayer 3 of the first NMOS area N1. The first mask pattern M1 may includesilicon oxide and/or silicon nitride.

Referring to FIG. 5B, the method may include removing the exposed firstgate barrier layer 3 and the first mask pattern M1 by performing anetching process, forming a second gate barrier layer 4 on the first gatebarrier layer 3 on the first NMOS area Ni and the gate insulating layer2 of the second NMOS area N2, and forming a second mask pattern M2 whichexposes the second gate barrier layer 4 of the first NMOS area N1 andcovers the second gate barrier layer 4 of the second NMOS area N2.

The second gate barrier layer 4 may be conformally formed on the firstgate barrier layer 3 in the first NMOS area N1 and the gate insulatinglayer 2 in the second NMOS area N2 by performing a deposition process.The second gate barrier layer 4 may include at least one of titaniumnitride (TiN), tantalum nitride (TaN), titanium oxynitride (TiON),tantalum oxynitride (TaON), titanium aluminum nitride (TiAlN), tantalumaluminum nitride (TaAlN), titanium silicon nitride (TiSiN), titaniumaluminum oxynitride (TiAlON), tantalum aluminum oxynitride (TaAlON), andtitanium silicon oxynitride (TiSiON).

In embodiments of the inventive concept, the second gate barrier layer 4may include a metal material different than the first gate barrier layer3. For example, the second gate barrier layer may include titaniumsilicon nitride (TiSiN).

A vertical thickness of the first gate barrier layer 3 may besubstantially the same as a vertical thickness of the second gatebarrier layer 4.

The second mask pattern M2 may include silicon oxide and/or siliconnitride.

Referring to FIG. 5C, the method may include removing the exposed thesecond gate barrier layer 4 and the second mask pattern M2 by performingan etching process.

Referring to FIG. 5D, the method may include sequentially forming a workfunction metal layer 5, a barrier capping layer 6, and a gate electrodelayer 7 on the first gate barrier layer 3 and the second gate barrierlayer 4.

The work function metal layer 5 may be conformally formed on the firstgate barrier layer 3 and the second gate barrier layer 4 by performing adeposition process. The work function metal layer 5 may include at leastone of titanium aluminum (TiAl), titanium aluminum oxide (TiAlO),titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN),titanium aluminum oxynitride (TiAlON), titanium aluminum carbonitride(TiAlCN), titanium aluminum oxycarbonitride (TiAlOCN), and a combinationthereof.

The barrier capping layer 6 may be conformally formed on the workfunction metal layer 5 by performing a deposition process. The barriercapping layer 6 may include at least one of titanium nitride (TiN),tantalum nitride (TaN), titanium oxynitride (TiON), tantalum oxynitride(TaON), titanium aluminum nitride (TiAlN), tantalum aluminum nitride(TaAlN), titanium silicon nitride (TiSiN), titanium aluminum oxynitride(TiAlON), tantalum aluminum oxynitride (TaAlON), and titanium siliconoxynitride (TiSiON).

The gate electrode layer 7 may be formed on the barrier capping layer 6by performing a deposition process. The gate electrode layer 7 mayinclude at least one of titanium nitride (TiN), tantalum nitride (TaN),tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt),and nickel-platinum alloy (Ni—Pt).

Referring again to FIGS. 2A and 2B, the method may include forming afirst NMOS gate pattern 130A in the first NMOS area N1 and a second NMOSgate pattern 130B in the second NMOS area N2 by patterning the gateelectrode layer 7, the barrier capping layer 6, the work function metallayer 5, the first gate barrier layer 3, the second gate barrier layer4, the gate insulating layer 2, and the interfacial insulating layer 1.

The method may further include forming source/drain areas 127 in theactive regions 120 located at both sides of the first and second NMOSgate patterns 130A and 130B. The forming of the source/drain areas 127may include removing portions of the active regions 120 at both sides ofthe first and second NMOS gate patterns 130A and 130B, and formingepitaxial layer on the active regions 120 by performing a selectiveepitaxial growth (SEG) process. Accordingly, the active regions 120between the source/drain areas 127 may be channel areas 125. That is,the channel areas 125 may vertically overlap the first and second NMOSgate patterns 130A and 130B.

FIGS. 6A to 6F illustrate cross-sectional views taken along lines I-I′,II-II′, V-V′, and VI-VI′ of FIG. 1. FIGS. 6A to 6F are views regardingonly an NMOS area, but it may be simultaneously or separately performedin the same method with respect to a PMOS area. In embodiments of theinventive concept, detailed descriptions of the same contents as thoseof the above-described embodiments will be omitted.

Referring to FIG. 6A, a method of fabricating the semiconductor devicein accordance with embodiments of the inventive concept may includepreparing a substrate 201, forming device isolation regions 210 definingactive regions 220 on the substrate 201, forming a sacrificial gatepattern 230S crossing the active regions 220 on the substrate 201, andforming gate spacers 260 on side surfaces of the sacrificial gatepatterns 230S. The substrate 201 may include a first NMOS area N1 inwhich the NMOS transistor having a low threshold voltage is disposed,and the second NMOS area N2 in which the NMOS transistor having a highthreshold voltage is disposed.

The sacrificial gate pattern 230S may include sacrificial gateinsulating patterns 231 s on surfaces of the active regions 220,sacrificial gate electrode patterns 233 s on the sacrificial gateinsulating patterns 231 s, and sacrificial gate capping patterns 235 son the sacrificial gate electrode patterns 233 s.

The sacrificial gate insulating patterns 231 s may include at least oneof a natural oxide layer formed on the surfaces of the active regions220, a silicon oxide layer formed using a thermal oxidation process, anda silicon oxide layer deposited using a deposition process such as anALD process. The sacrificial gate electrode patterns 233 s may includepolysilicon. The sacrificial gate capping patterns 235 s may includesilicon nitride.

The forming of the gate spacer 260 may include conformally forming aspacer material layer on upper and side surfaces of the sacrificial gatepatterns 230S, the exposed the active regions 220, and the deviceisolation region 210 by performing a deposition process, and removing aportion of the spacer material layer by performing an etch-back process.The spacer material layer may include at least one of silicon nitride(SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), siliconoxycarbonitride (SiOCN), and silicon borocarbonitride (SiBCN)

The method may further include forming source/drain areas 227 in theactive regions 220 at both sides of the sacrificial gate patterns 230S.The forming of the source/drain areas 227 may include removing portionsof the active regions 220 at both sides of the sacrificial gate patterns230S, and forming epitaxial layer on the active regions 220 byperforming an SEG process. Accordingly, the active regions 220 betweenthe source/drain areas 227 may be channel areas 225.

Referring to FIG. 6B, the method may include forming an interlayerinsulating layer 270 configured to cover upper surfaces of thesource/drain areas 227, upper surfaces of the device isolation regions210, and an outer side surface of the gate spacer 260, and forming gatepattern spaces GS exposing an inner side surface of the gate spacer 260and surfaces of the active regions 220 by removing the sacrificial gatepatterns 230S using an etching process.

The forming of the interlayer insulating layer 270 may include formingthe interlayer insulating layer 270 covering the source/drain areas 227,the device isolation regions 210, and the sacrificial gate patterns 230Sby performing a deposition process, and removing the interlayerinsulating layer 270 on the sacrificial gate patterns 230S to exposesurfaces of the sacrificial gate capping patterns 235 s of thesacrificial gate patterns 230S by performing a planarization processsuch as a chemical mechanical polishing (CMP) process. Accordingly, anupper surface of the interlayer insulating layer 270 may besubstantially coplanar with an upper surface of the sacrificial gatepattern 230S and an upper surface of the gate spacer 260. The interlayerinsulating layer 270 may include silicon oxide.

Referring to FIG. 6C, the method may include forming a interfacialinsulating layer 1, a gate insulating layer 2, and a first gate barrierlayer 3 in the gate pattern spaces GS, and forming a first mask patternM1 configured to cover the first gate barrier layer 3 of the first NMOSarea Ni and expose the first gate barrier layer 3 of the second NMOSarea N2.

The interfacial insulating layer 1 may be formed on surfaces of theactive regions 220 exposed through the gate pattern spaces GS. Theinterfacial insulating layer 1 may include at least one of a naturaloxide layer formed on the surfaces of the active regions 220, a siliconoxide layer formed using a thermal oxidation process, and a siliconoxide layer deposited using a deposition process such as an ALD process.

The gate insulating layer 2 may be conformally formed on the exposedinner side surface of the gate spacer 260, the surface of theinterfacial insulating layer 1, the upper surface of the gate spacer260, and the upper surface of the interlayer insulating layer 270. Thegate insulating layer 2 may include at least one of high-k dielectricinsulators, such as hafnium oxide (HfO), aluminum oxide (AlO), zirconiumoxide (ZrO), lanthanum oxide (LaO), and another metal oxide.

The first gate barrier layer 3 may be conformally formed on the gateinsulating layer 2 by performing a deposition process. The first gatebarrier layer 3 may include at least one of titanium nitride (TiN),tantalum nitride (TaN), titanium oxynitride (TiON), tantalum oxynitride(TaON), titanium aluminum nitride (TiAlN), tantalum aluminum nitride(TaAlN), titanium silicon nitride (TiSiN), titanium aluminum oxynitride(TiAlON), tantalum aluminum oxynitride (TaAlON), and titanium siliconoxynitride (TiSiON). As an example, the first gate barrier layer 3 mayinclude titanium nitride (TiN).

Referring to FIG. 6D, the method may include removing the exposed firstgate barrier layer 3 in the second NMOS area N2 by performing an etchingprocess, removing the first mask pattern M1, conformally forming asecond gate barrier layer 4 on the first gate barrier layer 3 on thefirst NMOS area N1 and the gate insulating layer 2 of the second NMOSarea N2, and forming a second mask pattern M2 configured to expose thesecond gate barrier layer 4 of the first NMOS area N1 and cover thesecond gate barrier layer 4 of the second NMOS area N2.

The second gate barrier layer 4 may include a metal material differentthan the first gate barrier layer 3. For example, the second gatebarrier layer may include titanium silicon nitride (TiSiN).

Referring to FIG. 6E, the method include removing the exposed secondgate barrier layer 4 in the first NMOS area N1 by performing an etchingprocess and removing the second mask pattern M2.

Referring to FIG. 6F, the method include conformally forming a workfunction metal layer 5, a barrier capping layer 6, and a gate electrodelayer 7 on the first gate barrier layer 3 and the second gate barrierlayer 4 by performing a deposition process.

Referring again to FIGS. 3A and 3B, the method may include forming afirst NMOS gate pattern 230A in the first NMOS area N1 and a second NMOSgate pattern 230B in the second NMOS area N2 by removing the gateelectrode layer 7, the barrier capping layer 6, the work function metallayer 5, the first gate barrier layer 3, the second gate barrier layer4, the gate insulating layer 2 on the interlayer insulating layer 270 byperforming a planarization process such as a CMP process.

FIGS. 7A to 7F illustrate cross-sectional views taken along lines I-I′,II-II′, V-V′, and VI-VI′ of FIG. 1. FIGS. 7A to 7F are views regardingonly an NMOS area, but it may be simultaneously or separately performedin the same method with respect to a PMOS area. In this embodiment ofthe inventive concept, detailed descriptions of the same content asthose of the above-described embodiments will be omitted.

Referring to FIG. 7A, a method of fabricating the semiconductor devicein accordance with embodiments of the inventive concept may includepreparing a substrate 301, forming fin active regions 320, deviceisolation regions 310, and sacrificial gate patterns 330S on thesubstrate 301, and forming gate spacers 260. The substrate 301 mayinclude a first NMOS area N1 and a second NMOS area N2.

The forming of the fin active regions 320 on the substrate 301 mayinclude forming a recess mask on the substrate 301, and forming the finactive regions 320 and a trench 311 by selectively etching the substrate301 using the recess mask as an etching mask. The fin active regions 320may protrude from the substrate 301.

The forming of the device isolation regions 310 may include filling thetrench 311 with device isolation insulator 312, removing a portion ofthe device isolation insulator 312 to expose a surface of the recessmask by performing a planarization process such as a CMP process, andforming device isolation regions 310 configured to have upper surfaceslocated at a lower level than upper surfaces of the fin active regions320 by performing an etch-back process. The device isolation regions 310may include silicon oxide.

The device isolation regions 310 may fill a lower portion of the trench311. Accordingly, portions of the fin active regions 320 may protrudefrom surfaces of the device isolation regions 310. Side and uppersurfaces of the protruding portions of the fin active regions 320 may becovered by the first and second NMOS gate patterns 330A and 330B whichwill be described later.

The sacrificial gate patterns 330S may each include a sacrificial gateinsulating pattern 331 s, a sacrificial gate electrode pattern 333 s anda sacrificial gate capping pattern 335 s which are sequentially stackedon surfaces of the fin active regions 320.

The method may further include forming source/drain areas 327 on the finactive regions 320 at both sides of the sacrificial gate patterns 330S.The fin active region 320 between the source/drain areas 327 may bechannel areas 325.

Referring to FIG. 7B, the method may include forming an interlayerinsulating layer 370 configured to cover upper surfaces of thesource/drain areas 327, upper surfaces of the device isolation regions310, and an outer side surface of the gate spacer 360, and forming gatepattern spaces GS exposing an inner side surface of the gate spacer 360and surfaces of the fin active regions 320 by removing the sacrificialgate patterns 330S by performing an etching process.

Referring to FIG. 7C, the method may include forming a interfacialinsulating layer 1, a gate insulating layer 2, and a first gate barrierlayer 3 in the gate pattern spaces GS, and forming a first mask patternM1 configured to cover the first gate barrier layer 3 of the first NMOSarea N1 and expose the first gate barrier layer 3 of the second NMOSarea N2.

Referring to FIG. 7D, the method may include removing the exposed firstgate barrier layer 3 in the second NMOS area N2 by performing an etchingprocess, removing the first mask pattern M1, conformally forming asecond gate barrier layer 4 on the first gate barrier layer 3 on thefirst NMOS area N1 and the gate insulating layer 2 of the second NMOSarea N2, and forming a second mask pattern M2 configured to expose thesecond gate barrier layer 4 of the first NMOS area N1 and cover thesecond gate barrier layer 4 of the second NMOS area N2.

Referring to FIG. 7E, the method may include removing the exposed secondgate barrier layer 4 in the first NMOS area N1 by performing an etchingprocess, and removing the second mask pattern M2.

Referring to FIG. 7F, the method may include conformally forming a workfunction metal layer 5, a barrier capping layer 6, and a gate electrodelayer 7 on the first gate barrier layer 3 and the second gate barrierlayer 4 by performing a deposition process.

Referring again to FIGS. 4A, the method may include forming a first NMOSgate pattern 330A in the first NMOS area N1 and a second NMOS gatepattern 330B in the second NMOS area N2 by removing the gate electrodelayer 7, the barrier capping layer 6, the work function metal layer 5,the first gate barrier layer 3, the second gate barrier layer 4, and thegate insulating layer 2 on the interlayer insulating layer 270 byperforming a planarization process such as a CMP process.

FIG. 8 is a schematic diagram illustrating a semiconductor module 2200,in accordance with an embodiment of the inventive concept. Referring toFIG. 8, the semiconductor module 2200 in accordance with embodiments ofthe inventive concept includes a processor 2220 and semiconductordevices 2230 mounted on a module substrate 2210. The processor 2220 orthe semiconductor devices 2230 may include at least one of thesemiconductor devices 100A to 300D according to the various embodimentsof the inventive concept. Conductive input/output terminals 2240 may bedisposed on at least one side of the module substrate 2210.

FIGS. 9 and 10 are schematic block diagrams illustrating electronicsystems, in accordance with embodiments of the inventive concept.

Referring to FIG. 9, the electronic system 2300 in accordance withembodiments of the inventive concept includes a body 2310, a displayunit 2360, and an external apparatus 2370. The body 2310 includes amicroprocessor unit 2320, a power supply 2330, a function unit 2340,and/or a display controller unit 2350. The body 2310 may be a systemboard or motherboard including a printed circuit board (PCB) and/or acase. The microprocessor unit 2320, the power supply 2330, the functionunit 2340, and the display controller unit 2350 may be mounted ordisposed on an upper surface or an inside of the body 2310. The displayunit 2360 may be disposed on the upper surface of the body 2310 or aninside/outside of the body 2310. The display unit 2360 may display animage processed by the display controller unit 2350. For example, thedisplay unit 2360 may include a liquid crystal display (LCD), an activematrix organic light emitting diode (AMOLED), or various display panels.The display unit 2360 may include a touch screen. Accordingly, thedisplay unit 2360 may include an input/output function. The power supply2330 may supply a current or voltage to the microprocessor unit 2320,the function unit 2340, the display controller unit 2350, etc. The powersupply 2330 may include a rechargeable battery, a socket for a dry cell,or a voltage/current converter. The microprocessor unit 2320 may receivea voltage from the power supply 2330 to control the function unit 2340and the display unit 2360. For example, the microprocessor unit 2320 mayinclude a central processing unit (CPU) or an application processor(AP). The function unit 2340 may include a touch-pad, a touch-screen, avolatile/nonvolatile memory, a memory card controller, a camera, alighting, an audio and video playback processor, a wirelesstransmission/reception antenna, a speaker, a microphone, a UniversalSerial Bus (USB) port, and other units having various functions. Themicroprocessor unit 2320 or the function unit 2340 may include at leastone of the semiconductor devices 100A to 300D according to the variousembodiments of the inventive concept.

Referring to FIG. 10, an electronic system 2400 in accordance withembodiments of the inventive concept includes a microprocessor 2414, amemory 2412, and a user interface 2418, which perform data communicationusing a bus 2420. The microprocessor 2414 may include a CPU or an AP.The electronic system 2400 may further include a random access memory(RAM) 2416 which directly communicates with the microprocessor 2414. Themicroprocessor 2414 and/or the RAM 2416 may be assembled in a singlepackage. The user interface 2418 may be used to input data to or outputdata from the electronic system 2400. For example, the user interface2418 may include a touch-pad, a touch-screen, a keyboard, a mouse, ascanner, a voice detector, a cathode ray tube (CRT) monitor, an LCD, anAMOLED, a plasma display panel (PDP), a printer, a lighting, or variousother input/output devices. The memory 2412 may store codes foroperating the microprocessor 2414, data processed by the microprocessor2414, or external input data. The memory 2412 may include a memorycontroller, a hard disk, or a solid state drive (SSD). Themicroprocessor 2414, the RAM 2416, and/or the memory 2412 may include atleast one of the semiconductor devices 100A to 300D according to thevarious embodiments of the inventive concept.

The semiconductor device according to embodiments of the inventiveconcept may include gate barrier patterns including metal materials thathave the different work functions from each other. As a result, a gatepattern having different effective work function in the semiconductordevice can be implemented.

Other various effects have been described in the above detaileddescriptions.

As is traditional in the field of the inventive concepts, embodimentsmay be described and illustrated in terms of blocks which carry out adescribed function or functions. These blocks, which may be referred toherein as units or modules or the like, are physically implemented byanalog and/or digital circuits such as logic gates, integrated circuits,microprocessors, microcontrollers, memory circuits, passive electroniccomponents, active electronic components, optical components, hardwiredcircuits and the like, and may optionally be driven by firmware and/orsoftware. The circuits may, for example, be embodied in one or moresemiconductor chips, or on substrate supports such as printed circuitboards and the like. The circuits constituting a block may beimplemented by dedicated hardware, or by a processor (e.g., one or moreprogrammed microprocessors and associated circuitry), or by acombination of dedicated hardware to perform some functions of the blockand a processor to perform other functions of the block. Each block ofthe embodiments may be physically separated into two or more interactingand discrete blocks without departing from the scope of the inventiveconcepts. Likewise, the blocks of the embodiments may be physicallycombined into more complex blocks without departing from the scope ofthe inventive concepts.

Although a few example embodiments have been described, those skilled inthe art will readily appreciate that many modifications are possiblewithout departing from the novel teachings and advantages. Accordingly,all such modifications are intended to be included within the scope ofthis inventive concept as defined in the claims.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate having a first conductivity type transistorarea, the first conductivity type transistor area including a first areaand a second area; and a first gate pattern on the first area and asecond gate pattern on the second area, wherein the first gate patternincludes a first gate insulating pattern on the first area, a first gatebarrier pattern on the first gate insulating pattern, and a first workfunction metal pattern on the first gate barrier pattern, the secondgate pattern includes a second gate insulating pattern on the secondarea, a second gate barrier pattern on the second gate insulatingpattern, and a second work function metal pattern on the second gatebarrier pattern the first gate barrier pattern includes a metal materialdifferent than the second gate barrier pattern, and the first gatebarrier pattern and the second gate barrier pattern each comprisemulti-layer patterns, and a layer pattern of the first gate barrierpattern includes different metal materials than a corresponding layerpattern of the second gate barrier pattern.
 2. The semiconductor deviceof claim 1, wherein the multi-layer patterns of the first gate barrierpattern include a first lower gate barrier pattern on the first gateinsulating pattern, a first intermediate gate barrier pattern on thefirst lower gate barrier pattern, and a first upper gate barrier patternon the first intermediate gate barrier pattern, and the multi-layerpatterns of the second gate barrier pattern include a second lower gatebarrier pattern on the second gate insulating pattern, a secondintermediate gate barrier pattern on the second lower gate barrierpattern, and a second upper gate barrier pattern on the secondintermediate gate barrier pattern.
 3. The semiconductor device of claim2, wherein the first lower gate barrier pattern and the second lowergate barrier pattern include different metal materials, the firstintermediate gate barrier pattern and the second intermediate gatebarrier pattern include a same metal material, and the first upper gatebarrier pattern and the second upper gate barrier pattern include a samemetal material.
 4. The semiconductor device of claim 2, wherein thefirst lower gate barrier pattern and the second lower gate barrierpattern include a same metal material, the first intermediate gatebarrier pattern and the second intermediate gate barrier pattern includea same metal material, and the first upper gate barrier pattern and thesecond upper gate barrier pattern include different metal materials. 5.The semiconductor device of claim 2, wherein the first lower gatebarrier pattern and the second lower gate barrier pattern include a samemetal material, the first intermediate gate barrier pattern and thesecond intermediate gate barrier pattern include different metalmaterials, and the first upper gate barrier pattern and the second uppergate barrier pattern include a same metal material.
 6. The semiconductordevice of claim 1, wherein the semiconductor substrate further comprisesa second conductivity type transistor area including a third area and afourth area.
 7. The semiconductor device of claim 6, further comprising:a third gate pattern on the third area, the third gate pattern includinga third gate insulating pattern on the third area, a third gate barrierpattern on the third gate insulating pattern, and a third work functionmetal pattern on the third gate barrier pattern; and a fourth gatepattern on the fourth area, the fourth gate pattern including a fourthgate insulating pattern on the fourth area, a fourth gate barrierpattern on the fourth gate insulating pattern, and a fourth workfunction metal pattern on the fourth gate barrier pattern, wherein thethird gate barrier pattern includes a metal material different than thefourth gate barrier pattern.
 8. The semiconductor device of claim 1,wherein the first gate insulating pattern, the second gate insulatingpattern, the first gate barrier pattern, the second gate barrierpattern, the first work function metal pattern and the second workfunction metal pattern have U-shapes.
 9. The semiconductor device ofclaim 8, further comprising: gate spacers on outer side surfaces of thefirst gate pattern and the second gate pattern; and an interlayerinsulating layer configured to cover outer side surfaces of the gatespacers and a surface of the semiconductor substrate.
 10. Thesemiconductor device of claim 1, wherein the first area includes a firstactive region having a first fin configured to protrude from a surfaceof the semiconductor substrate in a direction perpendicular to thesemiconductor substrate, the second area includes a second active regionhaving a second fin configured to protrude from the surface of thesemiconductor substrate in the direction perpendicular to thesemiconductor substrate, the first gate pattern covers an upper surfaceand side surfaces of the first fin, and the second gate pattern coversan upper surface and side surfaces of the second fin.
 11. Thesemiconductor device of claim 1, wherein the first gate barrier patternand the second gate barrier pattern include at least one of titaniumnitride (TiN), tantalum nitride (TaN), titanium oxynitride (TiON),tantalum oxynitride (TaON), titanium aluminum nitride (TiAlN), tantalumaluminum nitride (TaAlN), titanium silicon nitride (TiSiN), titaniumaluminum oxynitride (TiAlON), tantalum aluminum oxynitride (TaAlON), andtitanium silicon oxynitride (TiSiON).
 12. The semiconductor device ofclaim 1, wherein the first work function metal pattern and the secondwork function pattern include at least one of titanium aluminum (TiAl),titanium aluminum oxide (TiAlO), titanium aluminum carbide (TiAlC),titanium aluminum nitride (TiAlN), titanium aluminum oxynitride(TiAlON), titanium aluminum carbonitride (TiAlCN), titanium aluminumoxycarbonitride (TiAlOCN), and a combination thereof.
 13. Thesemiconductor device of claim 1, wherein the first gate pattern furtherincludes a first barrier capping pattern on the first work functionmetal pattern and a first gate electrode pattern on the first barriercapping pattern and wherein the second gate pattern further includes asecond barrier capping pattern on the second work function metal patternand a second gate electrode pattern on the second barrier cappingpattern
 14. A semiconductor device comprising: a semiconductor substratehaving a first area in which a first NMOS transistor is formed, a secondarea in which a second NMOS transistor having a different thresholdvoltage than the first NMOS transistor is formed, a third area in whicha first PMOS transistor is formed, and a fourth area in which a secondPMOS transistor having a different threshold voltage from the first PMOStransistor is formed; and a first NMOS gate pattern on the first area, asecond NMOS gate pattern on the second area, a first PMOS gate patternon the third area, and a second PMOS gate pattern on the fourth area,wherein a first NMOS gate barrier pattern of the first NMOS gate patternand a second NMOS gate barrier pattern of the second NMOS gate patterninclude different metal materials from each other, a first PMOS gatebarrier pattern of the first PMOS gate pattern and a second PMOS gatebarrier pattern of the second PMOS gate pattern include different metalmaterials from each other, and the first, second, third and fourth areaseach include an active region having a fin configured to protrude from asurface of the semiconductor substrate in a direction perpendicular tothe semiconductor substrate, and the first NMOS gate pattern, the secondNMOS gate pattern, the first PMOS gate pattern and the second PMOS gatepattern respectively cover an upper surface and side surfaces of thefins in the first, second, third and fourth areas.
 15. The semiconductordevice of claim 14, wherein the first NMOS transistor has a thresholdvoltage lower than the second NMOS transistor, and the first PMOStransistor has a threshold voltage lower than the second PMOStransistor, and wherein the first PMOS gate barrier pattern and thesecond NMOS gate barrier pattern include a same metal material, and thesecond PMOS transistor and the first NMOS transistor include a samemetal material.
 16. A semiconductor device comprising: a semiconductorsubstrate including a first area having a first NMOS transistor and asecond area having a second NMOS transistor that has a differentthreshold voltage than the first NMOS transistor; a first gateinsulating pattern on the first area and a second gate insulatingpattern on the second area; a first gate barrier pattern on the firstgate insulating pattern and a second gate barrier pattern on the secondgate insulating pattern; a first work function metal pattern on thefirst gate barrier pattern and a second work function metal pattern onthe second gate barrier pattern; and a first barrier capping pattern onthe first work function metal pattern and a second barrier cappingpattern on the second work function pattern, wherein the first gatebarrier pattern includes a metal material having a different workfunction than the second gate barrier pattern, and the first gatebarrier pattern and the second gate barrier pattern each comprisemulti-layer patterns, and a layer pattern of the first gate barrierpattern includes different metal materials than a corresponding layerpattern of the second gate barrier pattern.
 17. The semiconductor deviceof claim 16, wherein the first barrier capping pattern and the secondbarrier capping pattern include a same metal material.
 18. Thesemiconductor device of claim 16, wherein the first barrier cappingpattern and the second barrier capping pattern include at least one oftitanium nitride (TiN), tantalum nitride (TaN), titanium oxynitride(TiON), tantalum oxynitride (TaON), titanium aluminum nitride (TiAlN),tantalum aluminum nitride (TaAlN), titanium silicon nitride (TiSiN),titanium aluminum oxynitride (TiAlON), tantalum aluminum oxynitride(TaAlON), and titanium silicon oxynitride (TiSiON).
 19. Thesemiconductor device of claim 16, wherein a vertical thickness of thefirst gate barrier pattern is substantially the same as a verticalthickness of the second gate barrier pattern.
 20. The semiconductordevice of claim 16, further comprising: a first gate electrode patternon the first barrier capping pattern; and a second gate electrodepattern on the second barrier capping pattern.